1. Technical Field
This disclosure relates to processors, and more particularly to memory.
2. Description of the Related Art
Most processors today use a cache memory to increase efficiency of memory accesses and to reduce the time to fetch instructions or data from a system memory. As processor speeds increase, cache access time becomes increasingly more important. Moreover, for a cache memory read access that misses in the translation lookaside buffer (TLB), at least a portion of the virtual address (VA) is converted to a physical address (PA) to access the cache. The translation process takes a non-trivial amount of time. In some cases, portions of the physical address (e.g., some PA bits) may arrive later than other portions of the PA/VA. This can be problematic in some cache architectures.
Further, cache array design may be a significant factor in the overall design area required to implement an integrated circuit, as well as its operating frequency and power consumption. Mobile processor applications may be particularly sensitive to power consumption issues, in that power consumption is ordinarily directly related to battery life. Improving the power efficiency of cache arrays may improve a processor's overall power consumption.